The present invention relates to binary MOS carry-look-ahead parallel adders which are integrated using enhancement-mode insulated-gate field-effect transistors of the same conductivity type (N- or P-channel) and with which two numbers represented in the n-digit binary code can be added, the carry signal of each digit position being formed by carry look-ahead.
Parallel adders of this kind are described in a book by A. Shah et al, "Inegrierte Schaltungen In Digitalen Systemen", Vol. 2, Basel, 1977, pages 94 to 103. According to the formulas given on pages 94 and 95, the logic equation for the formation of the k-th carry signal Ck is:
Ck=Dk+EkDj+EkEjDi+ . . . +EkEjEi . . . ElDO+EkEjEi . . . ElEOC(-1),
with the following relation holding for the indices i, j, k: EQU k=j+1=i+2= . . .
For the D and E signals the following equations hold: EQU Dk=Ak.multidot.Bk,
where the dot means logic AND, and EQU Ek=Ak+Bk,
where the plus sign means logic OR.
Furthermore, an S'k signal to be regarded as a subtotal signal, is defined as follows: EQU S'k=Ak.sym.Bk=Dk.multidot.Ek,
where the encircled plus sign means modulo-2 addition, i.e., EXCLUSIVE-OR. Finally the following logic equation holds for the sum signal Sk of each binary digit: EQU Sk=S'K.sym.Cj,
i.e., the sum signal of the k-th digit position is obtained by forming the EXCLUSIVE-OR of the subtotal signal S'k of this digit with the carry signal of the next lower-order position.
FIG. IX.7 on page 96 of the above reference shows the logic diagram of a parallel adder for two four-digit binary numbers which is constructed on these principles. Four logic gates are connected in series with respect to the signal flow between the inputs for the individual digit signals Ak, Bk and the corresponding outputs for the sum signals Sk. The term "gate" is understood here to be a logic element which has a load of its own.
Page 97 of the above-mentioned book contains information on bipolar integrated circuits constructed in accordance with FIG. IX.7 of page 96 and on commercially available bipolar integrated circuits. Direct application of the fundamental principles of conventional carry-look-ahead parallel adders, which are explained there with reference to bipolar integrated circuits, to integrated circuits using insulated-gate field-effect transistors, i.e., to so-called MOS circuits, is not readily possible because MOS technology differs widely from bipolar technology in some respects.